1. Field of the Invention
This invention relates to a semiconductor device and its manufacturing method, especially to a semiconductor device with a penetrating electrode and its manufacturing method.
2. Description of the Related Art
Chip size package (referred to as CSP hereinafter) has recently been gathering attention as a three-dimensional packaging technology and as a new packaging technology. CSP is a small package with the outside dimensions almost the same as those of a semiconductor chip.
A BGA (Ball Grid Array) type semiconductor device with a penetrating electrode has been known as a CSP. The BGA type semiconductor device has a penetrating electrode connected with a pad electrode piercing through a semiconductor substrate. This type of semiconductor device has a plurality of conductive terminals disposed in a matrix configuration with a ball-shape, and made of metal such as welding on the backside of the device.
Each of the conductive terminals is connected to a wiring pattern on a circuit substrate (for example, a print substrate) when the semiconductor device is built into an electronic device. The BGA type semiconductor device has an advantage, because the device can accommodate a plurality of conductive terminals, leading to a minimization of the size, unlike other CSP type semiconductor device such as SOP (small outline package) or QFP (quad flat package) that has a lead pin protruding from side surface.
Next, the manufacturing method of the BGA type semiconductor device with the penetrating electrode of prior arts will be explained. A pad electrode is formed on a semiconductor substrate with a first insulating film between them. Next, a via hole reaching the pad electrode from the backside of the semiconductor device is formed by etching the semiconductor substrate. Then, a second insulating film exposing the pad electrode at the bottom of the via hole is disposed on the backside of the semiconductor device including the inside of the via hole.
A penetrating electrode electrically connected to the pad electrode that is exposed at the bottom of the via hole is formed on the second insulating film inside of the via hole. A wiring layer connected to the penetrating electrode is simultaneously formed on the second insulating film formed at the backside of the semiconductor substrate. Then, a protecting film is disposed at the backside of the semiconductor substrate including the wiring layer and a part of the protecting film is opened up to expose a part of the wiring layer. It is possible to further form conductive terminals on the wiring layer. Then, the semiconductor substrate is cut into a plurality of semiconductor chips through dicing. The related technology is disclosed, for example, in Japanese Patent Application Publication No. 2003-309221.